It is often desirable to incorporate decoupling capacitors (or “decaps”) in semiconductor components to electrically decouple one region of logic transistors from another such region. In most traditional decap designs, the ground node is connected to a lightly- or moderately-doped N-well and biased in accumulation. In this way, the low N-well resistance improves high-frequency response of the component while providing the desired decoupling characteristics.
Known decap designs are unsatisfactory in a number of respects, however. For example, logic circuits often require N-wells to be electrically coupled to the supply voltage. A space is therefore required between the logic N-well and the decap N-well to prevent leakage current between the wells or, in some extreme cases, latch-up. Furthermore, logic transistors close to the edge of the N-well are affected by what is termed the “well proximity effect” (WPE), which gives rise to an undesirable source of variation with respect to other transistors in the circuit.
Furthermore, because it is desirable to place the decap structure close to the surrounding logic, it is common to incorporate the decap within the standard cell rows. This, however, can result in an alteration of the N-well shape and an interruption of the regular pattern of the array.
Accordingly, it is desirable to provide improved decap designs that can be incorporated into standard cell rows while reducing variations in the well proximity effect experienced by surrounding logic devices.